The features used to create integrated circuits (ICs) are continually decreasing in feature size and spacing and/or increasing in density. Challenges arise however as topography varies across the substrate. For example, one region of a substrate may include a dense array of features while nearby area has an isolated feature. This topography can cause overlying layers to be deposited with non-uniform thickness, which may impact further processing.
Furthermore, understanding the variations in topography and the resulting non-uniform thickness of overlying areas prior to fabrication may allow for reduced cost, improved efficiency and like benefits. Therefore, what is needed is a feed-forward method of formation of a uniform layer on a semiconductor substrate overlying varying topography.